upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 483

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16-Bit
Timer/
Event
Counter
00
Function
Capture register
timing retention
Valid edge
setting
One-shot pulse
output by
software trigger
One-shot pulse
output with
external trigger
One-shot pulse
output function
Operation of
OVF00 flag
Conflicting
operations
Timer operation
Details of
Function
The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and
CR010) are not guaranteed after 16-bit timer/event counter 00 has been stopped.
Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and
TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0, respectively,
and then stopping timer operation. The valid edge is set using bits 4 and 5
(ES000 and ES001) of prescaler mode register 00 (PRM00).
Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not input the external trigger again while the one-shot pulse is being output.
To output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI000 pin or its alternate-function port pin, resulting
in the output of a pulse at an undesired timing.
The OVF00 flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM00 and CR000, the mode in which clear & start
occurs at the TI000 pin valid edge, or the free-running mode
Even if the OVF00 flag is cleared before the next count clock is counted (before
TM00 becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is
re-set newly so this clear is not valid.
When a read period of the 16-bit timer capture/compare register (CR000/CR010)
and a capture trigger input (CR000/CR010 used as capture register) conflict, the
priority is given to the capture trigger input. The data read from CR000/CR010 is
undefined.
Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit
timer capture/compare register 010 (CR010).
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI000/TI010 pins are not acknowledged.
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI000 valid edge. In the mode
in which clear & start occurs on a match between the TM00 register and CR000
register, one-shot pulse output is not possible because an overflow does not
occur.
CR000 is set to FFFFH
TM00 is counted up from FFFFH to 0000H.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
Cautions
p. 158
p. 158
p. 158
p. 158
p. 158
p. 159
p. 159
p. 159
p. 160
p. 160
p. 160
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