upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 498

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

498
Reset
Function
Clock
Monitor
Power-on-
clear
Circuit
(POC)
Low-
voltage
Detector
(LVI)
Function
RESF: Reset
control flag
register
CLM: Clock
monitor mode
register
Clock monitor
operation
Power-on-clear
circuit functions
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage
detection
register
LVIS: Low-
voltage
detection level
selection
register
When used as
reset
Cautions for
Low-Voltage
Detector
Details of
Function
Do not read data by a 1-bit memory manipulation instruction.
Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or
the internal reset signal.
If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit
1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Waiting for the oscillation stabilization time is not required when the external RC
oscillation clock is selected as the high-speed system clock by the option byte.
Therefore, the CPU clock can be switched without reading the OSTC value.
However, the clock monitor starts operation after the oscillation stabilization time
(OSTS register reset value = 05H (2
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
The supply voltage is V
subsystem clock is used, but be sure to use the product in a voltage range of 2.2
to 5.5 V because the detection voltage (V
The supply voltage is V
but be sure to use the (A1) grade products in a voltage range of 2.25 to 5.5 V
because the detection voltage (V
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Be sure to clear bits 4 to 7 to 0.
Clear all port pins after the supply voltage (V
voltage (V
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If supply voltage (V
internal reset signal is not generated.
In a system where the supply voltage (V
vicinity of the LVI detection voltage (V
on how the low-voltage detector is used.
(1) When used as reset
(2) When used as interrupt
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (a) below.
Interrupt requests may be frequently generated. Take action (b) below.
APPENDIX D LIST OF CAUTIONS
LVI
) after POC release in the (A1) grade products.
User’s Manual U16961EJ4V0UD
DD
)
DD
DD
detection voltage (V
= 2.0 to 5.5 V when the internal oscillation clock or
= 2.0 to 5.5 V when the internal oscillation clock is used,
POC
) of the POC circuit is 2.0 to 2.25 V.
16
Cautions
/f
LVI
XP
POC
DD
DD
), the operation is as follows depending
)) has elapsed.
POC
) fluctuates for a certain period in the
), the system may be repeatedly reset
) fluctuates for a certain period in the
) of the POC circuit is 2.1 V 0.1 V.
DD
LVI
) exceeds the preset detection
) when LVIMD is set to 1, an
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