upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 493

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Serial
Interface
UART6
Function
ASIS6:
Asynchronous
serial interface
reception error
status register 6
ASIF6:
Asynchronous
serial interface
transmission
status register 6
CKSR6: Clock
selection
register 6
BRGC6: Baud
rate generator
control register
6
ASICL6:
Asynchronous
serial interface
control register
6
Details of
Function
The operation of the PE6 bit differs depending on the set values of the PS61 and
PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6).
The first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 6 (RXB6) but discarded.
If data is read from ASIS6, a wait cycle is generated. Do not read data from
ASIS6 when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT.
To transmit data continuously, write the first transmit data (first byte) to the TXB6
register. After that, be sure to check that the TXBF6 flag is “0”. If so, write the
next transmit data (second byte) to the TXB6 register. If data is written to the
TXB6 register while the TXBF6 flag is “1”, the transmit data cannot be guaranteed.
To initialize the transmission unit upon completion of continuous transmission, be
sure to check that the TXSF6 flag is “0” after generation of the transmission
completion interrupt, and then execute initialization. If initialization is executed
while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the base clock is the internal oscillation clock, the operation of serial interface
UART6 is not guaranteed.
Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when
rewriting the MDL67 to MDL60 bits.
The baud rate is the output clock of the 8-bit counter divided by 2.
ASICL6 can be refreshed (the same value is written) by software during a
communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or
bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that
communication is started by the refresh operation because bit 6 (SBRT6) of
ASICL6 is cleared to 0 when communication is completed (when an interrupt
signal is generated). However, do not set both SBRT6 and SBTT6 to 1 by a
refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until
INST6 occurs since SBTT6 has been set (1) ), because it may re-trigger SBF
reception or SBF transmission.
In the case of an SBF reception error, the mode returns to the SBF reception
mode. The status of the SBRF6 flag is held (1).
Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of
ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF
reception is completed (before an interrupt request signal is generated).
The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0
after SBF reception has been correctly completed.
Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6
(TXE6) of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before
SBF transmission is completed (before an interrupt request signal is generated).
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
Cautions
p. 273
p. 273
p. 273
p. 273
p. 274
p. 274
p. 275
p. 276
p. 276
p. 276
p. 277
p. 278
p. 278
p. 278
p. 278
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