SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 10

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

Terminal Functions
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Ungated inputs DCKEn, DODTn
Chip Select
gated inputs
Chip Select
inputs
Re-driven
outputs
Parity input
Parity error
output
Clock inputs
Feedback
Clock
Clock Outputs
Miscellaneous
inputs
Signal Group
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
DAn, DBAn, DRAS,
DCAS, DWE
DCS0, DCS1
DCS2, DCS3
QxAn, QxBAn,
QxCSn, QxCKEn,
QxODTn, QxRAS,
QxCAS, QxWE
PAR_IN
ERROUT
CK, CK
FBIN, FBIN
FBOUT, FBOUT
Yn, Yn
RESET
MIRROR
QSCEN
Signal Name
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Outputs
1.25V/1.35V/1.5V
CMOS Inputs
Open drain
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Inputs
1.25V/1.35V/1.5V
CMOS Outputs
1.25V/1.35V/1.5V
CMOS Outputs
CMOS
CMOS
CMOS
3
3
3
Type
1
1
1
1
1
1
1
2
2
2
DRAM corresponding register function pins not associated with
Chip Select.
DRAM corresponding register inputs, re-driven only when either
chip select is LOW. If both chip selects are low the register maintains
the state of the previous input clock cycle at its outputs
DRAM corresponding register Chip Select signals. These pins
initiate DRAM address/command decodes, and as such exactly one
will be low when a valid address/command is present which should
be re-driven.
DRAM corresponding register Chip Select signals when QuadCS
mode is enabled. DCS2 and DCS3 inputs are disabled when QuadCS
mode is disabled.
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock. x is A or B;
outputs are grouped as A or B and may be enabled or disabled via
RC0.
Input parity is received on pin PAR_IN and should maintain parity
across the Chip Select Gated inputs (see above), at the rising edge of
the input clock, one input clock cycle after corresponding data and
one or both chip selects are LOW.
When LOW, this output indicates that a parity error was identified
associated with the address and/or command inputs. ERROUT will
be active for two clock cycles, and delayed by 3 clock cycles to the
corresponding input data
Differential master clock input pair to the PLL; has weak internal
pull-down resistors (10KΩ~100KΩ) .
Feedback clock input
Feedback clock output
Re-driven Clock
Active low asynchronous reset input. When LOW, it causes a reset of
the internal latches and disables the outputs, thereby forcing the
outputs to float. Once RESET becomes high the Q outputs get
enabled and are driven LOW (ERROUT is driven high) until the first
access has been performed. RESET also resets the ERROUT signal.
Selects between two different ballouts for front or back operation.
When the MIRROR input is high, the device Input Bus Termination
(IBT) is turned off on all inputs, except the DCSn and DODTn
inputs.
Enables the QuadCS mode. The QSCEN input has a weak internal
pullup resistor (10KΩ - 100KΩ).
10
Description
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
7314/8