SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 60

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
The IBT control is also located in this control word, with two options of 100Ω or 150Ω which can be selected to adapt to
different system scenarios. At power-up, the SSTE32882KA1 IBT defaults to 100Ω. The system controller can reprogram the
termination resistance to 150Ω by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE, DCSn, DODTn, DCKEn, and
PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs do not have IBT.
If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are tied
together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs except the DCSn
and DODTn inputs.
The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can be driven
with an earlier signal compared to output clock and control in order to compensate for the slower signal travel speed. This
timing applies at all supported frequencies.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms
Total Effective IBT Value Tolerance
Mismatch Tolerance Between R-IBT-Up and R-IBT-Down
Mismatch Tolerance Between R-IBT-Up
1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%)
Effective IBT Tolerance Requirement
and R-IBT-Down
1
1
-10%
Min
60
ABS(5%)
Max
+10%
Max
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
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