SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 67

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Refer to “Calculating the virtual V
Enabling and disabling the CA outputs must not violate DRAM setup and hold time requirements. Therefore a t
may not occur earlier than the earliest (HL/LH) transition and a t
transition. Regular transitions are measured between CK/CK and CA/V
the state where the outputs are Hi-Z. To allow a correct and not overly conservative measurement a virtual V
is defined below. The calculation of the virtual V
point”. The voltage levels for y
t
signed in the formula.
1
and t
DCSn
CK
CK
2
covers a linear range and represents a typical slope of the waveform within the transition area. They have to be used
QxCSn
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Yn
Yn
Outputs
xa
and y
REF
xb
crossing point”.
are measured from V
t
V
DIS
Voltage waveforms address floating
OX
TT
crossing point is shown in the Figure, “Calculating the virtual V
virtual V
TT
EN
(V
TT
DD
transition may not occure later than the latest (HL/LH)
crossing
TT
/2) and should be selected such that the region between
crossings however a V
*
67
COMMERCIAL TEMPERATURE RANGE
t
EN
SSTE32882KA1
TT
V
OX
crossing is not available in
TT
V
OD
crossing point
DIS
TT
transition
crossing
7314/8