SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 41

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SSTE32882KA1

Manufacturer Part Number
SSTE32882KA1
Description
1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTE32882KA1AKG
Manufacturer:
IDT
Quantity:
20 000
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1 CK left out for better visibility.
The next figure shows the parity diagram with two consecutive parity-error occurrences and assumes the occurrence of both
parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN clocked in on the n+1 and n+2 input clock
cycles).
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by a clock cycle with no error
occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+2 input clock
cycles (PAR_IN clocked in on the n+1 and n+3 input clock cycles).
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by two input clock cycles with no error
occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+3 input clock
cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles).
Input
Input
Input
ERROUT
ERROUT
ERROUT
PAR_IN
PAR_IN
PAR_IN
CK
CK
CK
CA
CA
CA
(1)
(1)
(1)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Two Parity-Error Occurrences Separated by a Clock Cycle of no Error Occurrence
CA0
n
CA0
CA0
n
n
n+1
CA1
P0
Two Consecutive Parity-Error Occurrences
n+2
CA2
P1
ERROUT resulting from CA0 - P0, followed by 2nd error in CA2 - P2
n+1
n+1
Timing of clock, data and parity signals
CA1
CA1
P0
P0
n+3
CA3
P2
n+2
n+2
CA2
CA2
P1
P1
n+4
CA4
P3
n+5
CA5
P4
n+3
n+3
P2
P2
ERROUT resulting from CA0 - P0, followed by 2nd error in CA1 - P1
n+6
P5
ERROUT resulting from CA0 - P0
n+4
n+4
41
n+7
n+8
n+5
n+5
COMMERCIAL TEMPERATURE RANGE
n+9
SSTE32882KA1
n+6
n+6
7314/8

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