SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 45

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

REGISTER CKE POWER DOWN WITH IBT ON
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
To re-enable the register from this power saving state, valid logic levels are required at all register inputs when either or both
DCKEn inputs are driven high. Upon either DCKE0 or DCKE1 input going High, the register immediately starts driving High
on the appropriate QxCKEn signal. The QxCSn signals are driven High and QxODTn signals are driven Low. Other output
signals QxRAS, QxCAS, QxWE, and QxAddr are driven either high or low to ensure stable valid logic an all register outputs
when QxCKEn goes High. The register drives output signals to these levels for t
stabilized. After the input recievers are stabilized, the register output follow their corresponding input levels. When exiting
CKE power down mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable
register, when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The
register guarantees that input receivers are stabilized within t
shown in the previous diagram.
Upon entry into CKE Power Down Mode with IBT on, all register input buffers excluding IBT are disabled except for CK/CK,
DCKEn, DODTn, FBIN/FBIN, and RESET. The SSTE32882KA1 disables input buffers within tInDIS clocks after latching
both DCKEn Low. In order to eliminate any false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK
after the Address and Command input buffers are disabled. After tInDIS, the register can tolerate floating input except for
CK/CK, DCKEn, DODTn and RESET. The SSTE32882KA1 also disables all its output buffers except for Yn/Yn, QxODTn,
QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal.
The QxCKEn outputs are driven Low. The register output buffers are Hi-Z t
shown below.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
FIXEDOUTPUT
clocks after DCKEn input is driven High. This is
45
QDIS
FIXEDOUTPUT
clock after QxCKEn is driven Low. This is
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
to allow input receivers to be
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