SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 14

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

Parity, Low Power and Standby with QuadCS Mode Enabled
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
RESET
1
and high) when RESET is driven high.
2
and DCS1 are not included in this range. This column represents the sum of the number of A/C signals that are elec-
trically high.
3
ing data.
4
low, it stays latched low for exactly two clock cycles or until RESET is driven low.
5
6
H
H
H
H
H
H
H
L
It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low
Same three-cycle delay for ERROUT is valid for the de-select phase (see diagram)
The system is not allowed to pull CK and CK low while ERROUT is asserted.
PAR_IN arrivesone clock cycle afterdata to which it applies, ERROUT is issued three clock cycles after the fail-
A/C = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE. Inputs DCKE0, DCKE1, DODT0, DODT1, DCS0
This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
X or floating
DCS[3:0]
HHHH
XXXX
XXXX
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
X or floating X or floating X or floating X or floating
Inputs
L or H
CK
↑
↑
↑
↑
↑
L
1
H or L
CK
↓
↓
↓
↓
↓
L
1
Σ of A/C
14
Even
Even
Odd
Odd
X
X
X
2
PAR_IN
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
H
H
X
X
X
L
L
3
ERROUT
ERROUTn
Output
H
H
H
H
H
L
L
5
6
0
4
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