SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 50

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

DYNAMIC 1T/3T TIMING TRANSACTION AND OUTPUT INVERSION ENABLING/DISABLING
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Output Inversion is always enabled by default, after RESET is de-asserted, to conserve power and reduce simultaneous output
switching current. All A-outputs will follow the equivalent inputs, however the following B-outputs will be driven to the
complement of the matching A-outputs: QBA3 - QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2.
The Output Inversion feature is not used during DRAM MRS command access. When Output Inversion is disabled, all
corresponding A and B output drivers of the SSTE32882KA1 are driven to the same logic levels. Output Inversion must be
disabled when the MRS and EMRS commands must be issued to the DRAMs, for example, to assure that the same
programming is issued to all DRAMs in a rank.
With Output Inversion disabled during MRS access, in order to allow correct DRAM accesses with the consequently increased
simultaneous switching propagation delay the devices supports 3T timing. If this feature is invoked the device drives the
received data on its outputs for thee cycles instead of one. The only exceptions are the QxCS[n:0] outputs, which are the
QACS0, QACS1, QBCS0, and QBCS1 outputs in the QuadCS disabled mode and are QCS[3:0] in the QuadCS enabled mode.
When the device decodes the MRS command (DRAS=0, DCAS=0, DWE=0 and only one DCSn=0), it will disable the Output
Inversion function and pass the DRAM MRS command with an additional (one) clock delay on the appropriate QnCSx signal
to the DRAM. Back-to-back MRS command via the SSTE32882KA1 must have a minimum of three clock delays. The
SSTE32882KA1 will automatically enable Output Inversion if there is no DRAM MRS command three clocks after the
previous MRS command.
The inputs and outputs relationships for 1T timing and 3T timing are shown in the following three diagrams.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Dxxx input
Output Inversion Functional Diagram
50
QAxxx output
QBxxx output
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
7314/8