SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 37

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

Initialization
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
The SSTE32882KA1 can be powered-on at 1.5V, 1.35V or 1.25V. After the voltage transition, stable power is provided for a
minimum of 200 µs with RESET asserted.
When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced
to V
control registers are restored to their default states. The QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs must drive low
during reset, and all other outputs must float. As long as the RESET input is pulled low the register is in low power state and
input termination is not present.
A certain period of time (t
specification, the clock input signal must be stable, the register inputs DCS[n:0] must be pulled high to prevent any accidental
access to the control registers. Also, DCKE0 and DCKE1 inputs must be pulled low for the complete stabilization time (t
After reset and after the stabilization time (t
accepting and transfering data from the register inputs to the register outputs. The RESET input must always be held at a valid
logic level once the input clock is present.
To ensure defined outputs from the register before a stable clock has been supplied, the register must enter the reset state during
power-up. It may leave this state only after a low to high transition on RESET while a stable clock signal is present on CK and
CK.
In the DDR3 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore,
no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs
will float quickly (except for QACKE0, QACKE1, QBCKE0 and QBCKE1, which are driven low), relative to the time to
disable the differential input receivers. The figure below shows the system timing of clock and data during the initialization
sequence.
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
4 QxCKEn, QxODTn, QxCSn are not included in this range.
QxODT[0:1]
QxCS[n:0]
QxCKE[0:1]
DD
DCS[n:1]
DCKE[0:1]
DODT[0:1]
ERROUT
QxA/C
DA/C
RESET
Y[0:3]
CK
DCS0
/2, therefore the reference voltage (V
V
(1)
(2)
DD
(4)
(4)
(3)
(1)
Register drives CKE low until ready to transfer input signals
Step 0,1 Step 2
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
Register guarantees high logic
Register guarantees low logic
ACT
) before the RESET input is pulled high the reference voltage needs to be stable within
Step 3
Timing of clock and data during initialization sequence
t
INIT
= 200 μs
Step 4
Controller guarantees low logic
Controller guarantees valid logic
Controller guarantees valid logic
Controller guarantees high logic
Controller guarantees high logic
STAB
REF
) is not required to be stable during reset. In addition, when RESET is low, all
t
ACT
), the register must meet the input setup and hold specification before
Step 5
= 8 cycles
Register proper function and timing starting from here
PLL lock 6 μs
Step 6
37
High or Low
Step 7
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
STAB
7314/8
).