s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 15

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

6.1
April 20, 2009 S29NS-S_00_02
Data Address & Quantity Nomenclature
While the SSR or SSR Lock ASO areas are being programmed all banks switch to EA mode. During EA
mode no valid data may be read from a bank. This means that Simultaneous Read / Write is not supported for
SSR or SSR Lock programming. Code controlling the SSR or SSR Lock programming operation must be
executed from another memory, typically the code for this rarely performed programming operation is copied
to RAM memory for execution.
While a Configuration Register is being programmed only the bank containing the ASO switches to EA mode.
The ID/CFI and factory portion of the SSR ASO is not customer programmable.
During programming of any of these ASO areas, the Read Status Register command may be used with an
address that selects the sector address where the ASO is active. This will cause the status register contents
to overlay the ASO sector during the one read cycle for status that follows the Status Register Read
command. After the one status information read access, the ASO returns to the EA mode condition of no valid
data being readable. When the EA operation in the ASO is completed, the ASO information is again readable.
The Status Register Clear command may not be used while an ASO is entered. It is necessary to exit an ASO
before using the Status Register Clear command.
A Bit is a single One or Zero data value. A Byte is a group of 8 bits aligned on an 8 bit boundary. A Word is a
group of 16 bits aligned on a 16 bit boundary.
Throughout this document quantities of data are generally expressed in terms of byte units. Example:
most sectors have 128 Kilo Bytes of data and is written as 128 KBytes or 128KB. Addresses are also
expressed in byte units. A 128 KByte sector has an address range from 00000h to 1FFFFh Byte locations.
Byte units are used because most host systems and software for these systems use byte resolution
addresses. Software & hardware developers most often calculate code and data sizes in terms of bytes, so
this is more familiar terminology than describing data sizes in bits or words. In general, data units will not be
abbreviated if possible so that full unit names of Byte, Word, or bit are used. However, there may be cases
where capital B is used for byte units and lower case b is used for bit units, in situations where space is
limited such as in table column headers.
In some cases data quantities will also be expressed in word or bit units in addition to the quantity shown in
bytes. This may be done as an aid to readers familiar with prior device generation documentation which often
provided only word or bit unit values. Word units may also be used to emphasize that, in the memory devices
described in this documentation, data is always exchanged with the host system in word units. Each bus
cycle transfer of read or write data on the host system bus is a transfer 16 bits of data. A read bus cycle is
always a16 bit wide transfer of data to the host system whether the host system chooses to look at all the bits
or not. A write bus cycle is always a transfer of 16 bits to the memory device and the device will store all 16
bits to a register. In the case of a program operation all 16 bits of each word to be programmed will be stored
in the Flash array.
The address nomenclature used in this document is a shorthand form that shows addresses are formed from
a concatenation of high order bits, sufficient to select a Sector Address (SA = Flash Amax through A12), with
low order bits to select a location within the sector. When in Read mode and reading from the Flash Array the
entire address is used to select a specific word for asynchronous read or the starting word address of a burst
read.
Because data is always transferred in word units, the memory devices being discussed use only the address
signals from the system necessary to select words. The host system byte address uses system address a0 to
select bytes and a1 to select words. Flash memories with word wide data paths have traditionally started their
address signal numbering with A0 being the selector for words because a byte select input is not needed. So,
system address a-maximum to a1 are connected to Flash A-maximum to A0 (the documentation convention
here is to use lower case for system address signal numbering and upper case for Flash address signals).
Example: Flash word address A22 to A0 is connected to system byte address a23 to a1.
Many commands to the Flash device use an address which is a merge (concatenation) of the upper address
signals selecting the target sector with a specific bit pattern on the lower address signals. The specific bit
pattern changes for different write cycles in a command sequence. The specific sequence of bit patterns
reduce the chance that one or more misdirected or unintended write accesses will be interpreted as a valid
command sequence, as random writes are unlikely to have the correct bit patterns, on the correct address
signals, in the correct sequence. The bit patterns used are two complementary patterns of alternating ones
and zeros often referred to by the hex characters used to represent the patterns - AAAh and 555h.
D a t a
S h e e t
S29NS-S MirrorBit
( P r e l i m i n a r y )
®
Eclipse
™
Flash Family
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