s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 20

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

7.1
7.2
7.3
20
Bus Operations
Asynchronous Read
Synchronous Burst Read Mode and Configuration Register
Table 7.1
Legend
L = Logic 0, H = Logic 1, X = can be either V
Note
Data is delivered by a read operation only after the burst Initial Access Cycle count has been satisfied.
In order to use Asynchronous Read Mode the configuration register bit 15 must be set to 1. This is the default
after power-on or hardware reset.
To read data from the memory array, the system must first assert a valid address or address portions while
driving AVD# and CE# to V
OE# must remain at V
DQ15–A/DQ0 when CE# is Low, OE# is Low, AVD# is High, and the asynchronous access time is satisfied.
Address access time (t
access time (t
Asynchronous Read on page
The device is capable of synchronous, continuous sequential burst operation and linear burst operation of a
preset length.
The device natively operates on a 32-byte aligned group of 32-bytes, which is called a Cache Line (CL).
Every read operation accesses a CL in parallel then delivers to the data bus either as a single word from the
CL, when the bus is in asynchronous mode or, as a sequence of words from the CL in synchronous mode.
In continuous sequential burst read, when a cache line boundary is crossed, wait states, equal to the
programmable Initial Access Cycles value minus one, are inserted between the last word of a cache line and
the first word of the next cache line. The wait states are indicated by the RDY signal going Low.
The device supports fixed length linear burst read operations of 8 or 16 word length with wrap around at the 8
or 16 word aligned boundary. A burst access may be terminated early by taking CE# High.
In order to use Burst Read Mode the configuration register bit 15 must be set to 0. Other Configuration
Register values set various operational parameters associated with burst mode.
Prior to entering burst mode, the system should determine how many Initial Access Cycles (IAC) are needed
for the initial word of each burst access (see table below), what mode of burst operation is desired, how the
Standby (CE# deselect)
Hardware Reset
Asynchronous Address Latch
Asynchronous Read
Asynchronous Write Latched Data
Latch Starting Burst Address by
CLK
Burst Read and advance to next
address
Terminate current Burst cycle
(See Note)
describes the required state of each input signal for each bus operation.
Operation
CE
) is the delay from stable CE# to valid data at the outputs. See
IH
ACC
while the rising edge of AVD# latches the full address. The data appears on A/
S29NS-S MirrorBit
) is equal to the delay from stable addresses to valid output data. The chip enable
IL
. WE# must remain at V
60.
D a t a
CE#
H
X
L
L
L
L
L
IL
or V
OE#
IH
H
X
X
H
L
H
L
X
Asynchronous Mode Operations
.,
Table 7.1 Bus Operations
Synchronous Mode Operations
S h e e t
®
Eclipse
Standby & Reset
WE#
= rising edge.
X
X
X
H
H
H
X
™
IH
Flash Family
( P r e l i m i n a r y )
. CLK may toggle or remain at V
CLK
X
X
X
X
X
X
AVD#
H
X
X
H
H
L
X
A28-A16
Addr In
Addr In
X
X
X
X
X
X
S29NS-S_00_02 April 20, 2009
10.7.2, AC Characteristics–
Data Output Valid
Data Output Valid
A/DQ 15-A/DQ0
Data Input Valid
IL
Addr In
Addr In
High-Z
High-Z
High-Z
or V
IH
.
RESET#
H
H
H
H
H
H
H
L