s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 68

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

Legend
X = Don’t care
RA = Address of the location to be read.
RD = Read Data from location RA during read operation.
RR = Read Register value
PA = Address of the memory location to be programmed.
PD = Data to be programmed at location PA.
BA = Bank Address, bits sufficient to select a bank
SA = Sector Address, bits Amax through A12
CAP1 = Command Address Pattern 1 which is a merge (concatenation) of the upper address bits selecting the target sector with a first bit pattern. The Flash
address signals Amax to A12 must contain the sector address and A11 to A0 must contain a binary bit pattern of 0101_0101_0101. Note that the Flash address
signals express a word address. Flash address signals Amax to A0 are physically connected to system byte address signals amax to a1; example: Flash A22 to A0
connected to system a23 to a1. In terms of a system byte address (typically used in software) the upper address bits amax to a13 are merged with a binary bit
pattern of 0_1010_1010_1010 on a12 to a0.
CAP2 = Command Address Pattern 2 which is a merge (concatenation) of the upper address bits selecting the target sector with a second bit pattern. The Flash
address signals Amax to A12 must contain the sector address and A11 to A0 must contain a binary bit pattern of 1010_1010_1010. Note that the Flash address
signals express a word address. Flash address signals Amax to A0 are physically connected to system byte address signals amax to a1; example: Flash A22 to A0
connected to system a23 to a1. In terms of a system byte address (typically used in software) the upper address bits amax to a13 are merged with a binary bit
pattern of 1_0101_0101_0100 on a12 to a0. The LSB of byte address must be zero to ensure a word aligned address to place the command data in the lower order
byte lane.
CAP3 = Command Address Pattern 3 which is a merge (concatenation) of the upper address bits selecting the target sector with a third bit pattern. The Flash
address signals Amax to A12 must contain the sector address and A11 to A0 must contain a binary bit pattern of xxxx_0101_0101 (upper bits are don’t care). Note
that the Flash address signals express a word address. Flash address signals Amax to A0 are physically connected to system byte address signals amax to a1;
example: Flash A22 to A0 connected to system a23 to a1. In terms of a system byte address (typically used in software) the upper address bits amax to a13 are
merged with a binary bit pattern of x_xxxx_1010_1010 on a12 to a0.
SLA = SLR Low Address - Amax through A16 to select the lowest large sector address, A15 through A4 bits are don’t care, and A3 to A0 to select the boot sectors
to be locked.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. See
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing ID, Device ID, Indicator Bits), Configuration Register
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, and WD.
5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset
6. The Program Resume command is valid only during the Program Suspend mode/state.
7. The Erase Resume command is valid only during the Erase Suspend mode/state.
8. Command is valid when all banks are ready to read array data.
9. The total number of cycles in the command sequence is determined by the number of words written to the write buffer.
10. Entry commands are needed to enter a specific mode to enable instructions only available within that mode.
11. Must be the lowest word address of the cache line being programmed within the 512-byte write buffer page. This is not necessarily the lowest address of the
12. Subsequent addresses must fall within the same Sector and Page as the initial starting address.
68
read, Secure Silicon Region Read, SSR Lock Read, and 2nd cycle of Status Register Read
command to return the device to reading array data
page. Data words are loaded into the write page buffer in sequential order from lowest to highest address.
Secure Silicon Region Entry
(Note 8)(Note 10)
Write Buffer Load
Buffer to Flash
Secure Silicon Region Read
Secure Silicon Region Exit
Command Sequence
Section 7., Device Operations on page 19
(Note 9)
3-258
1
1
1
1
(SA) RA
CAP1
CAP1
CAP1
Addr
XXX
Table 11.1 Command Definitions (Sheet 2 of 2)
for description of bus operations.
S29NS-S MirrorBit
First
Secure Silicon Region Command Definitions
25 or BF
D a t a
Data
RD
88
29
F0
S h e e t
®
CAP2
Addr
Eclipse
Second
™
Flash Family
Bus Cycles (Notes 1–5)
( P r e l i m i n a r y )
Data
WC
(Note 11)
(SA) PA
Addr
Third
S29NS-S_00_02 April 20, 2009
Data
PD
(Note 12)
(SA) PA
Addr
Fourth
Data
PD