s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 25

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

7.4
April 20, 2009 S29NS-S_00_02
7.3.4.3
7.3.4.4
7.3.4.5
7.3.4.6
7.3.4.7
Status Register
When the appropriate number of Initial Access Cycles minus one have occurred, data is output after the rising
edge of the CLK. Valid data is then available after t
Subsequent words are output t
increments the internal address counter.
Note:For CR0[14:11], only the settings shown in
RDY Polarity
Configuration Register Zero, bit 10 (CR0.10), controls whether the RDY signal indicates valid data when High
or when Low. When this bit is zero the RDY signal indicates data is valid when the signal is Low. When this bit
is one the RDY signal indicates data is valid when the signal is High. The default for this bit is set to one after
power-on or a hardware reset.
RDY Timing
Configuration Register Zero, bit 8 (CR0.8), controls whether the RDY signal indicates valid data on the same
cycle that data is valid or one cycle before data is valid. When this bit is one the RDY signal indicates data is
valid in the same cycle the data is valid. When this bit is zero the RDY signal is asserted the cycle before data
is valid. The default for this bit is set to one after power-on or a hardware reset.
Output Drive Strength
Configuration Register Zero, bit 7 (CR0.7), controls whether the data outputs drive with full or half strength.
When this bit is zero the data outputs drive with full strength. When this bit is one the data outputs drive with
half strength. The default for this bit is cleared to zero after power-on or a hardware reset.
Burst Length
Configuration Register Zero bits 2 to 0 (CR0.[2:0]) define the length of burst read accesses. The bits from 2 to
0 are in most to least significant order. See the register table for code meaning & default value.
CR0 Default Value
The value in CR0 after power-on or hardware reset is DF48h.
The status of program and erase operations is provided by a single 16 bit status register. The Status Register
Read command is written followed by one read access of the status register information. The contents of the
status register overlays the sector selected by the Status Register Read command. The overlay is in effect for
one read access, specifically the next read access that follows the Status Register Read command, in the
sector selected by the command. Read accesses to other sectors return normal memory array or ASO data.
After the one status register access, the Status Register Read command selected sector returns to providing
memory array or ASO data when read.
The status register can be read in synchronous or asynchronous bus access mode. If read in synchronous
burst mode for more than one access cycle, the same status results will appear in each of the read cycles of
the burst access until the burst is terminated.
The status register contains bits related to the results - success or failure - of the most recently completed
Embedded Algorithms (EA): Erase Status (bit 5), and Program Status (bit 4), and Sector Locked Status (bit
1), and, bits related to the current state of any in process EA: Device Busy (bit 7), Erase Suspended (bit 6),
Program Suspended (bit 2), and Bank Status (bit 0). The current state bits indicate whether an EA is in
process, suspended, or completed.
The upper 8 bits (bits 15:8) are reserved. These have undefined high or low value that may change from one
status read to another. These bit should be treated as don’t care and ignored by any software reading status.
The Clear Status Register Command will clear to Zero the results related bits of the status register but will not
affect the current state bits.
D a t a
S h e e t
S29NS-S MirrorBit
BACC
( P r e l i m i n a r y )
after the rising edge of each successive clock cycle, which automatically
®
Eclipse
Table 7.2
BACC
™
Flash Family
and may be captured at the next rising edge.
are tested and supported.
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