s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 45

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

7.11
7.12
April 20, 2009 S29NS-S_00_02
Power On (Cold) Reset (POR)
Hardware (Warm) Reset
When power is first applied, with supply voltage below 1V, then rising to reach operating range minimum,
internal device configuration and warm reset activities are initiated. The device must not be accessed (CE# to
go High within t
period is optional. If RESET# is driven Low during POR it must satisfy the Hardware Reset parameters t
and t
operations the device will draw I
At the end of POR the device conditions are:
The RESET# input provides a hardware method of resetting the device to idle state. When RESET# is driven
low for at least a period of t
The device must not be accessed (CE# to remain High) for the duration of the reset operation (t
To ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is first asserted Low, the device draws I
V
See
SS
all internal configuration information is loaded
the device is in read mode
the Configuration Registers are at default values
the Status Register is at default value
the Sector Unlock Register is cleared
the Sector Lock Range registers are cleared
no sectors protected mode - however, ACC protection may be in effect
the Write Buffer is loaded with all ones
the internal Control Unit is in the idle state
terminates any operation in progress,
exits any ASO,
tristates all outputs,
resets the Configuration Registers,
resets the Status Register,
clears the Sector Unlock Register,
clears the Sector Lock Range registers,
sets the no sectors protected mode; however, ACC protection may be in effect
loads the Write Buffer with all ones,
reloads all internal configuration information necessary to bring all banks in the device to Read mode,
and resets the internal Control Unit to idle state.
the device will draw CMOS standby current (I
Figure 10.7
VRPH
. In which case the Reset operations will be completed at the later of t
D a t a
VCE
for timing diagrams
and remain High) for the duration of the POR operation (t
S h e e t
S29NS-S MirrorBit
RP
, the device immediately:
CC3
( P r e l i m i n a r y )
current.
®
Eclipse
CC3
™
Flash Family
).
CC4
during t
RPH
. If RESET# continues to be held at
VCS
VCS
). RESET# Low during this
or t
VRPH
. During Reset
RPH
).
RP
45