s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 30

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

7.7
30
Writing Commands/Command Sequences
Sample Code
The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the
system must drive CE# and WE# to V
an address, AVD# must be driven to V
latched on the rising edge of WE#. See the
that define each phase of a write bus operation to the device.
All write bus operations ignore the clock (CLK) input and all signal transitions must satisfy the asynchronous
write timing requirements. However, write bus operations may be performed while the device remains in
synchronous read mode as set in the Configuration register. Control, address, and data signal transitions may
be related to a clock, i.e. the system may remain in a synchronous bus mode so long as the signal transitions
to the device meet the asynchronous write timing requirements. But, the device does not support burst write
accesses. Each write must convey a single address and data word pair to the device. If the host system uses
a burst write bus protocol the burst should be terminated at a length of one word as the device will not capture
multiple words from a burst write access. Synchronous read burst in combination with synchronous write
operations (meeting the asynchronous write timing requirements) are illustrated in
Back Read and Write Combinations on page
Each write is a command or part of a command sequence to the device. The address provided in each write
operation may be a bit pattern used to help identify the write as a command to the device. The upper portion
of the address may also select the bank or sector the command operation is to be performed. A Bank
Address (BA) is the set of address bits required to uniquely select a bank. A Sector Address (SA) includes
Amax through A12 Flash address bits (system byte addresses a-max through a1). The data in each write
identifies the command operation to be performed or supplies information needed to perform the operation.
See
Characteristics on page 55
operation.
/* Example: Blank Check Command */
UINT16 *CAP1 = ((UINT16 *) sector_address + 0x555); /* Define CAP1 */
*CAP1 = 0x0033; /* Write Blank Check command */
/* poll for completion */
Cycle
11.1, Command Definitions on page 67
1
Write Blank Check Command to CAP1
Description
S29NS-S MirrorBit
represents the active current specification for a write (Embedded Algorithm)
D a t a
IL
IL
, and OE# to V
. Addresses are latched on the rising edge of AVD#, while data is
S h e e t
®
Table 7.1, Bus Operations on page 20
Eclipse
for a listing of the commands accepted by the device. I
62.
Operation
Write
™
Flash Family
IH
( P r e l i m i n a r y )
when providing an address and data. When latching
Sector Address + AAAh
Byte Address
S29NS-S_00_02 April 20, 2009
Sector Address + 555h
for the signal combinations
Section 10.7.4, Back to
Word Address
CC2
0033h
in
Data
DC