s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 198
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s908qc16vdse
Manufacturer Part Number
s908qc16vdse
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.S908QC16VDSE.pdf
(274 pages)
- Current page: 198 of 274
- Download datasheet (4Mb)
Timer Interface Module (TIM1)
TOF — TIM1 Overflow Flag Bit
TOIE — TIM1 Overflow Interrupt Enable Bit
TSTOP — TIM1 Stop Bit
TRST — TIM1 Reset Bit
198
This read/write flag is set when the counter reaches the modulo value programmed in the TIM1 counter
modulo registers. Clear TOF by reading the T1SC register when TOF is set and then writing a 0 to
TOF. If another TIM1 overflow occurs before the clearing sequence is complete, then writing 0 to TOF
has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF.
Writing a 1 to TOF has no effect.
This read/write bit enables TIM1 overflow interrupts when the TOF bit becomes set.
This read/write bit stops the counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the counter until software clears the TSTOP bit.
Setting this write-only bit resets the counter and the TIM1 prescaler. Setting TRST has no effect on
any other timer registers. Counting resumes from $0000. TRST is cleared automatically after the
counter is reset and always reads as 0.
1 = Counter has reached modulo value
0 = Counter has not reached modulo value
1 = TIM1 overflow interrupts enabled
0 = TIM1 overflow interrupts disabled
1 = Counter stopped
0 = Counter active
1 = Prescaler and counter cleared
0 = No effect
Reset:
Read:
Write:
Do not set the TSTOP bit before entering wait mode if the TIM1 is required
to exit wait mode. Also, when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
When using TSTOP to stop the timer counter, see if any timer flags are set.
If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the
flag, then setting TSTOP again.
Setting the TSTOP and TRST bits simultaneously stops the counter at a
value of $0000.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
Bit 7
TOF
0
0
Figure 16-4. TIM1 Status and Control Register (T1SC)
= Unimplemented
TOIE
6
0
TSTOP
5
1
TRST
NOTE
NOTE
4
0
0
3
0
0
PS2
2
0
PS1
1
0
Freescale Semiconductor
Bit 0
PS0
0
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