s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 94

• Manufacturer Part Number: s908qc16vdse
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Low-Voltage Inhibit (LVI)
The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared,
the default state at power-on reset, V
trip points are specified in
Characteristics.
Because the default LVI trip point after power-on reset is configured for low voltage operation, a system
requiring high voltage LVI operation must set the LVITRIP bit during system initialization. V
above the LVI trip rising voltage, V
go into LVI reset.
After an LVI reset occurs, the MCU remains in reset until V
Integration Module (SIM)
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
The LVI is enabled out of reset. The following bits located in the configuration register can alter the default
conditions.
9.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and
LVIRSTD must be set to disable LVI resets.
9.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets.
9.3.3 LVI Hysteresis
The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having
V
V
approximately equal to V
9.3.4 LVI Trip Selection
LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is
for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range
cannot be changed after initialization.
94
DD
TRIPR
•
•
•
•
fall below V
Setting the LVI power disable bit, LVIPWRD, disables the LVI.
Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (V
operating range.
. This prevents a condition in which the MCU is continually entering and exiting reset if V
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
section for the actual trip point voltages.
TRIPF
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
), the MCU will remain in reset until V
TRIPF
TRIPF
for the reset recovery sequence.
19.5 5-V DC Electrical Characteristics
) may be lower than this. See the Electrical Characteristics
DD
. V
to remain above the V
TRIPR
DD
TRIPR
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falls below the V
TRIPF
levels below the V
is greater than V
, for the high voltage operating range or the MCU will immediately
is configured for the lower V
NOTE
TRIPF
TRIPF
TRIPF
TRIPF
DD
level. In the configuration register, LVIPWRD
DD
rises above V
level, enabling LVI resets allows the LVI
by the typical hysteresis voltage, V
rises above the rising trip point voltage,
level, software can monitor V
and
19.8 3.3-V DC Electrical
DD
TRIPR
operating range. The actual
TRIPF
. See
Freescale Semiconductor
) for the higher V
Chapter 14 System
DD
DD
by polling
must be
DD
HYS
is
.
DD