s908qc16vdse Freescale Semiconductor, Inc, s908qc16vdse Datasheet - Page 201
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s908qc16vdse
Manufacturer Part Number
s908qc16vdse
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.S908QC16VDSE.pdf
(274 pages)
- Current page: 201 of 274
- Download datasheet (4Mb)
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
Freescale Semiconductor
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the T1SCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Writing a 1 to CHxF has no effect.
This read/write bit enables TIM1 interrupt service requests on channel x.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 16-10. TIM1 Channel 1 Status and Control Register (T1SC1)
Figure 16-11. TIM1 Channel 2 Status and Control Register (T1SC2)
Figure 16-12. TIM1 Channel 3 Status and Control Register (T1SC3)
Figure 16-9. TIM1 Channel 0 Status and Control Register (T1SC0)
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 4
CH0F
CH1F
CH2F
CH3F
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
CH0IE
CH1IE
CH2IE
CH3IE
6
0
6
0
6
0
6
0
MS0B
MS2B
5
0
5
0
0
5
0
5
0
0
MS0A
MS1A
MS2A
MS3A
4
0
4
0
4
0
4
0
ELS0B
ELS1B
ELS2B
ELS3B
3
0
3
0
3
0
3
0
ELS0A
ELS1A
ELS2A
ELS3A
2
0
2
0
2
0
2
0
TOV0
TOV1
TOV2
TOV3
1
0
1
0
1
0
1
0
CH0MAX
CH1MAX
CH2MAX
CH3MAX
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
Registers
201
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