s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 124

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Monitor ROM (MON)
12.3.7 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PA0.
If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and
can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to
send another eight bytes. If the reset was not a power-on reset, the security remains bypassed regardless
of the data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading FLASH locations returns undefined data,
and trying to execute code from FLASH causes an illegal address reset. After the host fails to bypass
security, any reset other than a power-on reset causes an endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits a break character signalling that
it is ready to receive a command.
124
V
RST
NOTE: 1 = Echo delay (2 bit times)
DD
PA0
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors. If FLASH is
unprogrammed, the eight security byte values to be sent are $FF, the
unprogrammed state of FLASH.
The MCU does not transmit a break character until after the host sends the
eight security bytes.
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
FROM HOST
FROM MCU
4096 + 32 CGMXCLK CYCLES
Figure 12-6. Monitor Mode Entry Timing
MC68HC908AZ32A Data Sheet, Rev. 2
1
24 BUS CYCLES (MINIMUM)
NOTE
NOTE
4
1
1
2
4
Freescale Semiconductor
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