s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 168

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peirpheral Interface (SPI)
17.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting
out on the MOSI pin under the control of the serial clock. (See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF (SPSCR), becomes set. At the same
time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal
operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and
control register and then reading the SPI data register. Writing to the SPI data register clears the SPTIE
bit.
17.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010) is clear. In slave mode the SPSCK
pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin
of the slave MCU must be at logic 0. SS must remain low until the transmission is complete. (See
Mode Fault
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it is transferred to the receive data
register, and the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave software then must
read the SPI data register before another byte enters the shift register.
168
17.13.2 SPI Status and Control
Error).
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See
SHIFT REGISTER
GENERATOR
BAUD RATE
MASTER MCU
Figure 17-3. Full-Duplex Master-Slave Connections
MC68HC908AZ32A Data Sheet, Rev. 2
MISO
MOSI
SPSCK
SS
Register). Through the SPSCK pin, the baud rate generator of the
NOTE
V
17.13.1 SPI Control
DD
Table
SPSCK
MISO
MOSI
SS
17-3).
Register.
SHIFT REGISTER
SLAVE MCU
Freescale Semiconductor
17.6.2