s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 194

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module A (TIMA)
Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the
PTF2/TCH4 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and
channel 5. The TIMA channel 4 registers initially control the pulse width on the PTF2/TCH4 pin. Writing
to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(4 or 5) that control the pulse width are the ones written to last. TASC4 controls and monitors the buffered
PWM function and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is
set, the channel 5 pin, PTF3/TCH5, is available as a general-purpose I/O pin.
18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
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1. In the TIMA status and control register (TASC):
2. In the TIMA counter modulo registers (TAMODH–TAMODL) write the value for the required PWM
3. In the TIMA channel x registers (TACHxH–TACHxL) write the value for the required pulse width.
4. In TIMA channel x status and control register (TASCx):
5. In the TIMA status control register (TASC) clear the TIMA stop bit, TSTOP.
period.
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter and prescaler by setting the TIMA reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
or PWM signals) to the mode select bits, MSxB–MSxA (see
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level (see
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908AZ32A Data Sheet, Rev. 2
NOTE
NOTE
Table
18-2).
Table
18-2).
Freescale Semiconductor