s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 225

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

20.5.2 Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode
after an external interrupt.
20.6 PIT During Break Interrupts
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
20.7 I/O Registers
The following I/O registers control and monitor operation of the PIT:
20.7.1 TIM Status and Control Register
The PIT status and control register:
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PIT status and control register (PSC)
PIT counter registers (PCNTH–PCNTL)
PIT counter modulo registers (PMODH–PMODL)
Enables PIT interrupt
Flags PIT overflows
Stops the PIT counter
Resets the PIT counter
Prescales the PIT counter clock
Address:
Reset:
Read:
Write:
$004B
POF
Bit 7
0
0
Figure 20-3. PIT Status and Control Register (PSC)
= Unimplemented
POIE
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
7.7.3 SIM Break Flag Control
PSTOP
5
1
PRST
4
0
0
3
0
0
PPS2
Register).
2
0
PPS1
1
0
PIT During Break Interrupts
PPS0
Bit 0
0
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