mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 63

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mt46v128m4bn

Manufacturer Part Number
mt46v128m4bn
Description
512mb X4, X8, X16 Ddr Sdram
Manufacturer
Micron Semiconductor Products
Datasheet

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Figure 36:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
x16 Data Output Timing –
DQ8–DQ15 and UDQS, collectively 6
DQ0–DQ7 and LDQS, collectively 6
Notes:
DQ (first data no longer valid) 4
DQ (first data no longer valid) 4
DQ (first data no longer valid) 7
DQ (first data no longer valid) 7
DQ (last data valid) 4
DQ (last data valid) 4
DQ (last data valid) 7
DQ (last data valid) 7
1.
2.
3. DQs transitioning after DQS transition define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transition and is
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t
t
transition, and ends with the last valid DQ transition.
byte, and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
UDQS 3
LDQS 3
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
CK
T1
t
DQSQ,
t
t HP
CL or
t
HP:
1
t
t
t
QH =
QH, and Data Valid Window
CH clock transition collectively when a bank is active.
63
t HP
t
1
HP -
t DQSQ
t QH 5
t DQSQ 2
T2
t QH 5
t
Data valid
2
QHS.
window
Data valid
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
window
t HP
T2
T2
T2
1
t DQSQ
T2n
t QH 5
t DQSQ 2
512Mb: x4, x8, x16 DDR SDRAM
Data valid
t QH 5
window
2
t HP
T2n
t
T2n
Data valid
T2n
DQSQ window. LDQS defines the lower
window
1
T2n
T2n
T2n
T3
t DQSQ
t QH 5
t DQSQ 2
t QH 5
t HP
Data valid
2
window
1
Data valid
window
T3
T3
T3
T3
©2000 Micron Technology, Inc. All rights reserved.
T3
T3
t
T3n
QH -
t DQSQ 2
t DQSQ
t QH 5
t QH 5
t HP
t
DQSQ.
1
Data valid
window
Data valid
2
window
T3n
T3n
T4
T3n
T3n
T3n
T3n
Operations

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