mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 72

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mt46v128m4bn

Manufacturer Part Number
mt46v128m4bn
Description
512mb X4, X8, X16 Ddr Sdram
Manufacturer
Micron Semiconductor Products
Datasheet

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Figure 45:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
WRITE-to-PRECHARGE – Uninterrupting
CK
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
and WRITE commands may be to different devices, in which case
the PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
72
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR
512Mb: x4, x8, x16 DDR SDRAM
T4
NOP
DON’T CARE
(a or all)
©2000 Micron Technology, Inc. All rights reserved.
Bank,
T5
PRE
t
WR is not required, and
TRANSITIONING DATA
t
RP
Operations
T6
NOP

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