mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 69
mt46v128m4bn
Manufacturer Part Number
mt46v128m4bn
Description
512mb X4, X8, X16 Ddr Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46V128M4BN.pdf
(83 pages)
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Figure 42:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
WRITE-to-READ – Uninterrupting
CK
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
commands may be to different devices, in which case
command could be applied earlier.
WTR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
69
T2n
T3
NOP
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WTR
512Mb: x4, x8, x16 DDR SDRAM
Bank a,
READ
Col n
T4
DON’T CARE
t
WTR is not required, and the READ
CL = 2
CL = 2
CL = 2
©2000 Micron Technology, Inc. All rights reserved.
T5
NOP
TRANSITIONING DATA
Operations
T6
NOP
DO
DO
DO
n
n
n
T6n