mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 78
mt46v128m4bn
Manufacturer Part Number
mt46v128m4bn
Description
512mb X4, X8, X16 Ddr Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46V128M4BN.pdf
(83 pages)
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Figure 51:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
COMMAND
ADDRESS
Case 1:
Case 2:
BA0, BA1
DQ
DQ
DQS
DQS
CK#
CKE
A10
DM
CK
t
t
AC (MIN) and
AC (MAX) and
6
6
Bank READ – with Auto Precharge
t
t
IS
IS
NOP
T0
Notes:
t
1
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The READ command can only be applied at T3 if
4. Enable auto precharge.
5.
6. DO n = data-out from column n; subsequent elements are provided in the programmed
7. Refer to Figure 35 on page 62, Figure 36 on page 63, and Figure 37 on page 64 for detailed
t
IS
Bank x
IS
Row
ACT
Row
T1
times.
t
order.
DQS and DQ timing.
RP starts only after
t
IH
IH
t
CK
t RCD, t RAP 3
t
t
RC
RAS
NOP
T2
1
t
CH
t
t
RAS has been satisfied.
CL
READ
t
IS
Bank x
4
Col n
T3
2,3
t
IH
t LZ (MIN)
CL = 2
78
NOP
T4
t
RPRE
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
LZ (MIN)
t
RPRE
512Mb: x4, x8, x16 DDR SDRAM
NOP
T5
t
t
DQSCK (MIN)
RAP is satisfied at T3.
DO
t
1
n
DQSCK (MAX)
t
AC (MIN)
DO
t
n
AC (MAX)
T5n
t RP 5
DON’T CARE
NOP
T6
1
©2000 Micron Technology, Inc. All rights reserved.
t
HZ (MAX)
T6n
t
RPST
t
RPST
NOP
T7
TRANSITIONING DATA
1
Operations
Bank x
T8
ACT
Row
Row