mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 74

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 47:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b.
2. An interrupted burst of 8 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to register DM.
6. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
t
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
74
t
WR
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
512Mb: x4, x8, x16 DDR SDRAM
(a or all)
Bank,
T4
PRE
DON’T CARE
T4n
T5
©2000 Micron Technology, Inc. All rights reserved.
NOP
TRANSITIONING DATA
t
RP
Operations
T6
NOP