ics9248-169 ETC-unknow, ics9248-169 Datasheet - Page 8

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ics9248-169

Manufacturer Part Number
ics9248-169
Description
Clock Synthesizer
Manufacturer
ETC-unknow
Datasheet
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-169 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
ICS9248-169
PCI_STOP# is an asynchronous input to the ICS9248-169. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-169 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
inside the ICS9248-169.
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