ics9248-127 ETC-unknow, ics9248-127 Datasheet - Page 13

• Manufacturer Part Number: ics9248-127
• Description: Frequency Generator Integrated Buffers Pentium/protm
• Manufacturer: ETC-unknow

Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-127. It is used to turn off the PCICLK [4:0] clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-127 internally. The minimum that the PCICLK [4:0] clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency
is one PCICLK clock.
inside the ICS9248.
(Free-running)
CPU_STOP#
PCI_STOP#
PCICLK_F
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
ICS9248-127