ics9248-66 ETC-unknow, ics9248-66 Datasheet - Page 2

• Manufacturer Part Number: ics9248-66
• Description: Single Chip Clock, Supports 133mhz
• Manufacturer: ETC-unknow

Pin Descriptions
General Description
4, 10, 16, 22, 28, 36
1, 7, 13, 19, 23, 26,
9, 11, 12, 14,
Pin number
15, 17, 18
20, 21, 24
37, 38, 41
29, 30
39, 42
2, 3
35
25
27
31
32
33
34
40
43
44
45
46
47
48
5
6
8
GNDLIOAPIC
VDDLIOAPIC
CPUCLK[0:3]
SEL 133/100#
PCICLK[1:7]
CPU_STOP#
GNDLCPU/2
VDDLCPU/2
PCI_STOP#
GNDLCPU
VDDLCPU
PCICLK_F
SPREAD#
3V66[0:2]
Pin name
REF(0:1)
SEL[0:1]
IOAPIC
48MHz
CPU/2
GND
VDD
PD#
X1
X2
OUT
PWR
OUT
OUT
PWR
OUT
Type
PWR
OUT
OUT
OUT
PWR
PWR
OUT
PWR
PWR
OUT
PWR
IN
IN
IN
IN
IN
IN
IN
Ground pins
14.318MHz reference clock outputs at 3.3V
Power pins 3.3V
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the
PCI_STOP# input.
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active..
This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz,
Low=100MHz
Fixed 48MHz clock output. 3.3V
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC, 3V66
and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread
modulation.
This asynchronous input powers down the chip when drive active(Low). The internal PLLs
are disabled and all the output clocks are held at a Low state.
This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0"
when driven active(Low). Does not affect the CPU/2 clocks.
This asynchronous input halts the PCICLK[1:7] at logic"0" when driven active(Low).
PCICLK_F is not affected by this input.
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL
133/100MHz.
Power pin for the CPUCLKs. 2.5V
Ground pin for the CPU/2 clocks.
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the
SEL 133/100# input pin.
Power pin for the CPU/2 clocks. 2.5V
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz.
Power pin for the IOAPIC outputs. 2.5V.
Power Groups:
Description
Advance Information
ICS9248-66