ics9248-56 ETC-unknow, ics9248-56 Datasheet - Page 2

• Manufacturer Part Number: ics9248-56
• Description: Mobile Main Clock With Real Time Spread, Supports 66.6 100mhz
• Manufacturer: ETC-unknow

ICS9248-56
Pin Descriptions
Pin number
5,6,9,10,11
23,24
12
13
14
15
16
17
18
19
20
21
22
25
26
27
28
1
2
3
4
7
8
TS#/48/24MHz
REF0/SEL48#
CPUCLK(1:0)
PCICLK (1:5)
CPU_STOP#
SEL 100/66#
Pin name
PCICLK_F
SPREAD#
PCI-Stop#
GNDREF
VDDREF
GNDPCI
VDDPCI
48 MHz
GND48
VDD48
GNDL
VDDL
GND
VDD
PD#
X1
X2
Output
Output
Output
Output
Output
Output
Output
Output
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
Ground for 14.318 MHz reference clock outputs
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for Pentium II 
Ground for PCI clock outputs
3.3 V power for the PCI clock outputs
3.3 V power for 48/24 MHz clocks
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing,
active high = normal operation
Ground for 48/24 MHz clocks
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selected cases.
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
Isolated 3.3 V power for core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Isolated ground for core
Ground for CPU clock outputs
2.5 V CPU clock outputs
2.5 V power for CPU clock outputs
Power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
3.3 V power for 14.318 MHz reference clock outputs.
2
Description