mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 150

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

USB 2.0 FS Module
There are 64-byte RAM buffer to share between the four data endpoints. User is required to specify the
buffer base address and the buffer size for each endpoint used. The buffer is separated in 8 bytes page,
therefore, there are 8 pages in total. For example, if 16 bytes of buffer is required for endpoint 1 and 16
bytes is required for endpoint 2, the buffer base address for endpoint 1 can be specified as %000, while
the buffer base address for endpoint 2 can be specified %010 and the buffer size SIZE[1:0] register should
be defined as %01 and %01 respectively.
11.3.5.1 OUT endpoint Data Transfer
The buffer size assigned to the endpoint is required to match with the endpoint definition specified in the
endpoint descriptor. On every packet of data transfer, data loaded to the endpoint buffers are started with
the buffer base address. If the data is valid, the complete packet is downloaded to the buffer RAM and
ACK is sent automatically. The packet size is reported to DSIZE register and the transfer complete flag
(TFRC) is set. User should wait until the data valid bit (DVALID) to be set before reading the data from
the buffers. Otherwise, if CRC error encountered, the data packet is ignored and no handshake is
returned.
11.3.5.2 IN endpoint Data Transfer
When IN packet is received by the module and DVALID bit is cleared, NAK is returned. If the IN packet is
corresponding to endpoint 0, user is required to write data to the dedicate 8 bytes registers, then DSIZE
should be updated before setting DVALID bit to send data via the next IN packet.
If the IN packet is corresponding to other endpoint 1 to 4, user is required to write data to corresponding
endpoint buffer indicated by the BASE pointer.
When the packet is transmitted successfully that ACK is returned from the host, DVALID bit is returned to
zero. Transfer complete flag (TFRC) is set to notify user for the next transfer.
11.4 Interrupt Source
There are two interrupt source reserved for the USB module.
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CONFIG_CHG
Table 11-3. Interrupt Source Table
TFRC0_OUT
RESUMEF
TFRC0_IN
USBRST
SUSPND
MC68HC908JW32 Data Sheet, Rev. 5
SETUP
TFRC1
TFRC2
TFRC3
TFRC4
Flag
SOF
USB Endpoint Interrupt
USB Endpoint Interrupt
USB Endpoint Interrupt
USB Endpoint Interrupt
USB Endpoint Interrupt
USB Endpoint Interrupt
USB System Interrupt
USB System Interrupt
USB System Interrupt
USB System Interrupt
USB System Interrupt
USB System Interrupt
Interrupt Source
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