mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 93

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.3.1 Entering Monitor Mode
Table 7-1
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
If V
frequency is a divide-by-two of the input clock. If PTC1 is high with V
mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC1 pin low when
entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V
to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage
is either V
divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
Freescale Semiconductor
V
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
2. External clock is derived by a 4.9152/9.8304 MHz off-chip oscillator
3. Monitor mode entry by IRQ = V
V
GND
IRQ
V
TST
1. IRQ = V
2. IRQ = V
(3)
TST
or
X
3)
DD
TST
lator circuit is bypassed.
(
–
–
is applied to IRQ and PTC1 is low upon monitor mode entry (above condition set 1), the bus
GND
V
V
V
RST
V
V
V
DD
or
or
or
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
TST
TST
TST
The external clock is 4.9152 MHz with PTC1 low
The external clock is 9.8304 MHz with PTC1 high
DD
DD
DD
or V
TST
TST
PTA2
SS
X
0
0
X
(PLL off):
(PLL off):
), then all port A pin requirements and conditions, including the PTC1 frequency
Table 7-1. Monitor Mode Signal Requirements and Options
PTA1
X
X
1
1
TST
PTA0
, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscil-
(1)
X
X
1
1
MC68HC908JW32 Data Sheet, Rev. 5
PTC1
X
X
0
1
External
Clock
4.9152
9.8304
MHz
MHz
X
X
(2)
2.4576
2.4576
Freq.
MHz
MHz
Bus
—
0
OFF
OFF
OFF
PLL
X
TST
Disabled
Disabled
Disabled
Enabled
applied to IRQ upon monitor
COP
Baud
9600
9600
Rate
—
0
Functional Description
No operation until
reset goes high
PTA1 and PTA2
voltages only
required if
IRQ = V
PTC1 determines
frequency divider
PTA1 and PTA2
voltages only
required if
IRQ = V
PTC1 determines
frequency divider
Enters user mode
TST
Comment
is applied
TST
TST
;
;
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