mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 87

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

6.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles
down to 32. This is ideal for applications using canned oscillators that do not require long start-up times
from stop mode.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status
register (SBSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Freescale Semiconductor
CGMXCLK
INT/BREAK
IAB
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
Figure 6-19. Stop Mode Recovery from Interrupt or Break
R/W
IDB
IAB
instruction.
STOP ADDR
STOP +1
Figure 6-18. Stop Mode Entry Timing
PREVIOUS DATA
MC68HC908JW32 Data Sheet, Rev. 5
STOP ADDR + 1
STOP + 2
STOP RECOVERY PERIOD
NOTE
NOTE
NEXT OPCODE
Figure 6-18
STOP + 2
SAME
shows stop mode entry timing.
SP
SAME
SP – 1
SAME
SAME
SP – 2
Low-Power Modes
SP – 3
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