mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 65

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.5 CGM Registers
The following registers control and monitor operation of the CGM:
5.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
PLLON — PLL On Bit
Freescale Semiconductor
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This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
1 = PLL on
0 = PLL off
PLL control register (PCTL) — (See
PLL bandwidth control register (PBWC) — (See
PLL multiplier select registers (PMSH and PMSL) — (See
PLL VCO range select register (PMRS) — (See
PLL reference divider select register (PMDS) — (See
Register.)
Address:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
$1090
PLLIE
Bit 7
0
Figure 5-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
MC68HC908JW32 Data Sheet, Rev. 5
PLLON
5
1
5.5.1 PLL Control
NOTE
BCS
4
0
5.5.4 PLL VCO Range Select
5.5.2 PLL Bandwidth Control
PRE1
3
0
5.5.5 PLL Reference Divider Select
Register.)
5.5.3 PLL Multiplier Select
PRE0
2
0
VPR1
5.3.8 Base Clock Selector
1
0
Register.)
Register.)
VPR0
Bit 0
0
CGM Registers
Registers.)
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