mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 204

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mc68hc908jw32

Manufacturer Part Number
mc68hc908jw32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Break Module (BRK)
18.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation.
structure of the break module.
18.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
18.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
18.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
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A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a logic 1 to the BRKA bit in the break status and control register.
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD
($FEFC and $FEFD in monitor mode)
IAB15–IAB0
Figure 18-2. Break Module Block Diagram
IAB15–IAB8
IAB7–IAB0
MC68HC908JW32 Data Sheet, Rev. 5
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
8-BIT COMPARATOR
8-BIT COMPARATOR
CONTROL
Figure 18-2
BREAK
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