mc68ec020 Freescale Semiconductor, Inc, mc68ec020 Datasheet - Page 220

• Manufacturer Part Number: mc68ec020
• Description: Microprocessors
• Manufacturer: Freescale Semiconductor, Inc

Example 2
Using the same instruction stream, the second example demonstrates the different effects
of instruction execution overlap on instruction timing when the same instructions are
positioned slightly differently in 32-bit memory:
The assumptions for example 2 (see Figure 8-4) are:
Although the total execution time of the instruction segment does not change in this
example, the individual instruction times are significantly different. This example
demonstrates that the effects of overlap are not only instruction-sequence dependent but
are also dependent upon the alignment of the instruction stream in memory.
8-6
EXECUTION TIME
1. The data bus is 32 bits,
2. The first instruction is prefetched from an even-word address,
3. Memory access occurs with no wait states, and
4. The cache is disabled.
INSTRUCTION
CONTROLLER
SEQUENCER
COUNTER
ACTIVITY
CLOCK
CLOCK
BUS
BUS
LEGEND:
1
IDLE
PERFORM
MOVE #1
MOVE.L D4,(A1)+
2
1) MOVE.L D4,(A1)+
2) ADD.L D4,D5
3) MOVE.L (A1),–(A2)
4) ADD.L D5,D6
WRITE TO (A1)+
Address
Figure 8-4. Processor Activity for Example 2
(4)
WRITE
3
PERFORM
ADD #2
4
5
CALCULATE
SOURCE EA
MOVE #3
M68020 USER’S MANUAL
BYTES n + 8
ADD.L D4,D5
PREFETCH
PREFETCH
n + 4
n + 8
6
n
(3)
7
IDLE
DESTINATION
8
CALCULATE
MOVE #3
READ FROM (A1)
MOVE #1
MOVE #3
EA
READ
9
•••
MOVE.L (A1),–(A2)
10
IDLE
(6)
11
PERFORM
MOVE #3
WRITE TO –(A2)
ADD #2
ADD #4
WRITE
12
•••
13
PERFORM
ADD #4
14
BYTES n + 12
ADD.L D5,D6
PREFETCH
PREFETCH
INSTRUCTION
15
(3)
NEXT
MOTOROLA
16
17