mc68ec020 Freescale Semiconductor, Inc, mc68ec020 Datasheet - Page 257

no-image

mc68ec020

Manufacturer Part Number
mc68ec020
Description
Microprocessors
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68ec020AA16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec020AA16
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc68ec020AA25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mc68ec020AA25
Quantity:
14
Company:
Part Number:
mc68ec020AA25
Quantity:
14
Part Number:
mc68ec020AA25R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec020FG25
Manufacturer:
FREESCALE
Quantity:
8 831
Part Number:
mc68ec020FG25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec020FG25
Manufacturer:
MOT
Quantity:
11
Part Number:
mc68ec020FG25
Manufacturer:
MOTOROL
Quantity:
20 000
Part Number:
mc68ec020RP16
Manufacturer:
PHILIPS
Quantity:
49
Part Number:
mc68ec020RP16
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
mc68ec020RP25
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
The major concern of a system designer is to design a CS interface that meets the AC
electrical specifications for both the MC68020/EC020 (MPU) and the MC68881/MC68882
(FPCP) without adding unnecessary wait states to FPCP accesses. The following
maximum specifications (relative to CLK low) meet these objectives:
Even though requirement (9-1) is not met under worst-case conditions, if the MPU AS is
loaded within specifications and the AS input to the FPCP is unbuffered, the requirement
is met under typical conditions. Designing the CS generation circuit to meet requirement
(9-2) provides the highest probability that accesses to the FPCP occur without
unnecessary wait states. A PAL 16L8 (see Figure 9-2) with a maximum propagation delay
of 10 ns, programmed according to the equations in Figure 9-3, can be used to generate
CS . For a 25-MHz system, t
design is used. Should worst-case conditions cause t
requirement (1), one wait state is inserted in the access to the FPCP; no other adverse
effects occur. Figure 9-4 shows the bus cycle timing for this interface. Refer to
MC68881UM/AD, MC68881/MC68882 Floating-Point Coprocessor User's Manual , for
FPCP specifications.
The circuit that generates CS must meet another requirement. When a nonfloating-point
access immediately follows a floating-point access, CS (for the floating-point access) must
be negated before AS and DS (for the subsequent access) are asserted. The PAL circuit
previously described also meets this requirement.
MOTOROLA
t
t
CLK
CLK
low to AS low
low to CS low
Figure 9-2. Chip Select Generation PAL
GND
CLK
FC2
FC1
FC0
A19
A18
A17
A16
AS
CLK
(MPU Spec 1 – MPU Spec 47A – FPCP Spec 19)
(MPU Spec 1 – MPU Spec 47A – FPCP Spec 19)
M68020 USER’S MANUAL
low to CS low is less than or equal to 10 ns when this
PAL 16L8
10 ns
CLK
V
NC
NC
NC
NC
A13
A14
CLKD
CS
A15
CC
low to AS low to exceed
(9-1)
(9-2)
9-3

Related parts for mc68ec020