mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 106
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mpc8378
Manufacturer Part Number
mpc8378
Description
Powerquicc Ii Pro Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8378.pdf
(127 pages)
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Package and Pin Listings
106
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
This output is actively driven during reset rather than being released to high impedance during reset.
These JTAG pins have weak internal pull-up P-FETs that are always enabled.
This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, “MPC837xE Design Checklist,” for more details.
These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
This pin must always be tied to GND using a 0 Ω resistor.
This pin must always be left not connected.
For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR
power using an 18.2 Ω resistor.
This pin must always be tied low. If it is left floating it may cause the device to malfunction.
See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
This pin must not be pulled down during PORESET.
Open or tie to GND.
Voltage settings are dependent on the frequency used; see
See AN3665, “MPC837xE Design Checklist,” for proper eTSEC termination.
Pull Down
Signal
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Table 72. TePBGA II Pinout Listing (continued)
Package Pin Number
B16, AH18
Table
3.
Pin Type
—
Power Supply
Freescale Semiconductor
—
Notes
7