mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 112

• Manufacturer Part Number: mpc8378
• Description: Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Clocking
1
2
23.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
112
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
CFG_CLKIN_DIV
0–1
nn
11
00
01
10
00
01
at reset
Low
Low
Low
Low
Low
Low
Low
Low
Low
Core PLL Configuration
Table 79
RCWL[COREPLL]
1
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
nnnn
0000
0001
0001
0001
0001
0001
2–5
should be considered as reserved.
Table 78. CSB Frequency Options for Agent Mode (continued)
Table 79
SPMF
0111
1000
1001
1010
1011
1100
1101
1110
1111
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 79. e300 Core PLL Configuration
6
0
n
0
0
0
1
1
Input Clock Ratio
(PLL off, csb_clk clocks core directly)
csb_clk :
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
7 : 1
8 : 1
9 : 1
core_clk : csb_clk Ratio
NOTE
PLL bypassed
2
1.5:1
1.5:1
n/a
1:1
1:1
1:1
175
200
225
250
275
300
325
350
375
25
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
(PLL off, csb_clk clocks core
33.33
233
267
300
333
367
400
Freescale Semiconductor
VCO Divider
PLL bypassed
directly)
n/a
2
4
8
2
4
66.67
1
2