mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 46

• Manufacturer Part Number: mpc8378
• Description: Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Secure Digital Host Controller (eSDHC)
11.2.1
Figure 27
11.2.1.1
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
No clock delay:
With clock delay:
This means that data can be delayed versus clock up to 11 ns in ideal case of t
11.2.1.2
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
46
t
t
DATA_DELAY
DATA_DELAY
provides the data and command output timing diagram.
Full-Speed Output Path (Write)
Full-Speed Write Meeting Setup (Maximum Delay)
Full-Speed Write Meeting Hold (Minimum Delay)
MPC8377E Pins
MPC8377E Pins
MPC8377E Pin
Output from the
SD CLK at the
the Card Pin
Input at the
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
t
SD CLK at
DATA_DELAY
+ 20 < 40 + t
< 11 + t
t
SFSKHOV
t
CLK_DELAY
Output Valid Time: t
Output Hold Time: t
CLK_DELAY
t
SFSKHOV
+ t
+ t
SFSCKL
CLK_DELAY
DATA_DELAY
< t
Figure 27. Full Speed Output Path
SFSCKL
+ t
< t
DATA_DELAY
t
SFSCK
SFSKHOV
SFSKHOX
SFSCK
Driving
+ t
Edge
t
DATA_DELAY
–
+ t
SFSKHOX
5
(Clock Cycle)
ISU
–
+ t
4
< t
CLK_DELAY
+ t
SFSCKL
ISU
+ t
DATA_DELAY
< t
t
t
SFSCKL
CLK_DELAY
ISU
+ t
–
t
t
CLK_DELAY
(5 ns)
ISU
SFSCKL
–
t
–
SFSKHOV
t
IH
Sampling
Edge
SFSCKL
t
IH
(5 ns)
Freescale Semiconductor
= 20 ns:
Eqn. 1
Eqn. 2
Eqn. 3
Eqn. 4