mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 109

• Manufacturer Part Number: mpc8378
• Description: Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

1
Table 74
conditions (see
Freescale Semiconductor
1
2
3
PCI Express1, 2
SATA1, 2
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR2 memory bus frequency (MCK)
DDR1 memory bus frequency (MCK)
Local bus frequency (LCLK n )
Local bus controller frequency ( lbc_clk )
PCI input frequency (CLKIN or PCI_CLK)
eTSEC frequency
Security encryption controller frequency
USB controller frequency
eSDHC controller frequency
PCI Express controller frequency
SATA controller frequency
Note:
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB modules,
SATA, and eSDHC will not exceed their respective value listed in this table.
the csb_clk frequency (depending on RCWL[LBIUCM]).
This only applies to I
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk , MCK,
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
provides the operating frequencies for the TePBGA II package under recommended operating
Unit
Table
2
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
C1 (I
3).
Parameter
2
C2 clock is not configurable).
3
Table 73. Configurable Clock Units (continued)
Table 74. Operating Frequencies for TePBGA II
2
2
1
Default Frequency
csb_clk/3
csb_clk/3
Off, c sb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
Minimum Operating
Frequency (MHz)
333
133
125
167
—
—
25
—
—
—
—
—
—
Options
Maximum Operating
Frequency (MHz)
800
400
200
333
133
400
400
200
200
200
400
200
66
Clocking
109