mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 110

• Manufacturer Part Number: mpc8378
• Description: Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Clocking
23.1
The system PLL is controlled by the RCWL[SPMF] parameter. The system PLL VCO frequency depends
on RCWL[DDRCM] and RCWL[LBCM].
system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in
110
Table 78
System PLL Configuration
show the expected frequency values for the CSB frequency for select csb_clk to
If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL
VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO
frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
Section 23, “Clocking,”
RCWL[SVCOD]
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
RCWL[SPMF]
0111–1111
0000
0001
0010
0011
0100
0101
0110
00
01
10
11
Table 75. System PLL Multiplication Factors
Table 76. System PLL VCO Divider
The LBIUCM, DDRCM, and SPMF parameters in the reset
Table 75
NOTE
shows the multiplication factor encodings for the
System PLL Multiplication Factor
VCO Division Factor
× 7 to × 15
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
4
8
2
1
Freescale Semiconductor
Table
76.
Table 77