mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet - Page 121

• Manufacturer Part Number: mpc8378
• Description: Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
25.3
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate
signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins
of the device.
25.4
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
Freescale Semiconductor
DD
/2. R
Connection Recommendations
Output Buffer DC Impedance
P
then becomes the resistance of the pull-up devices. R
0
for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
0
= (R
P
+ R
Figure 66. Driver Impedance Measurement
Data
N
)/2.
2
C).
Pad
P
R
R
is trimmed until the voltage at the pad equals
OVDD
OGND
N
P
P
and R
SW2
SW1
N
are designed to be close to each
DD
/2 (see
System Design Information
Figure
66). The
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