adav802 Analog Devices, Inc., adav802 Datasheet - Page 15

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
DAC SECTION
The ADAV802 has two DAC channels arranged as a stereo pair
with differential analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 128 steps
of 0.375dB per step. The DAC can receive data from the
playback or auxiliary input ports, the SRC, the ADC or the DIR.
Each analog output pin sits at a dc level of VREF, and swings 1.0
Vrms for a 0dB digital input signal. A single op-amp third-order
external low-pass filter is recommended to remove high-
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components. The
FILTD and FILTR pins should be bypassed by external
capacitors to AGND. The FILTD pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR can be used to
bias external op amps used to filter the output signals. For
applications where the FILTR is required to drive external op
amps which may draw more than 50µA or may have dynamic
load changes extra buffering should be used to preserve the
quality of the ADAV802 reference. The digital input data source
for the DAC can be selected from a number of available sources.
by programming the appropriate bits in the Datapath Control
register. Figure 7 shows how the digital data source and MCLK
source for the DAC are selected. Each DAC has an independent
volume register giving 256 steps of control with each step giving
approximately 0.375dB of attenuation. Each DAC also has a
peak level register which records the peak value of the digital
audio data. Reading the register clears the peak .
ANALOG
OUTPUT
DAC
DAC
SIGMA-DELTA
MODULATOR
MULTI-BIT
Figure 8. DAC Block Diagram
TO ZERO FLAG PINS
Rev. Pr G | Page 15 of 53
INTERPOLATOR
TO CONTROL
REGISTERS
Selecting a Sample Rate
Correct operation of the DAC is dependant upon the data rate
provided to the DAC, the master clock applied to the DAC and
the selected interpolation rate. By default the DAC assumes that
the MCLK rate is 256 times the sample rate which requires an 8
times oversampling rate. This combination is suitable for
sample rates up to 48kHz. For the case of a 96kHz data rate
which has a 24.576MHz MCLK (256 × f
DAC MCLK divider should be set to divide the MCLK by 2.
This will prevent the DAC engine being run too fast. To
compensate for the reduced MCLK rate the interpolator should
be selected to operate in 4 × (DAC MCLK = 128 × f
combinations can be selected for different sample rates.
VOLUME/MUTE
ZERO DETECT
DETECTOR
CONTROL
PEAK
Figure 7. Clock and data Path Control on the DAC
801-0007
801-0006
DIVIDER
MCLK
MCLK
DAC
DAC
INPUT
DAC
FROM DAC
DATAPATH
MULTIPLEXER
REG: 0x76
BITS 7-5
REG: 0x65
BITS 3-2
REG: 0x63
BITS 5-3
S
) associated with it the
AUXILIARY IN
PLAYBACK
DIR
ADC
ADAV802
S
). Similar