adav802 Analog Devices, Inc., adav802 Datasheet - Page 28

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adav802

Manufacturer Part Number
adav802
Description
Audio Codec For Recordable Dvd
Manufacturer
Analog Devices, Inc.
Datasheet
ADAV802
Table 26. SRC & Clock Control Register
ADDRESS = 0000000
SRCDIV1-0
CLK2DIV1-0
CLK1DIV1-0
MCLKSEL1-0
Table 27. SPDIF Loopback Control Register
ADDRESS = 0000011
TxMUX
SRCDIV1
7
Divides the SRC Master Clock
00 = The SRC Master Clock is not divided
01 = The SRC Master Clock is divided by 1.5
10 = The SRC Master Clock is divided by 2
11= The SRC Master Clock is divided by 3
Clock Divider for Internal Clock 2 (ICLK2)
00 = Divide by 1
01 = Divide by 1.5
10 = Divide by 2
11 = Divide by 3
Clock Divider for Internal Clock 1 (ICLK1)
00 = Divide by 1
01 = Divide by 1.5
10 = Divide by 2
11 = Divide by 3
Clock Selection for the SRC Master Clock
00 = Internal Clock 1
01 = Internal Clock 2
10 = PLL Recovered Clock (512 × f
11 = PLL Recovered Clock (256 × f
RES
7
Selects the source for SPDIF Output (DITOUT)
0 = SPDIF Transmitter - Normal Mode
1 = DIRIN - Loopback Mode
RES
6
SRCDIV
6
Rev. Pr G | Page 28 of 53
S
S
)
)
RES
5
CLK2-
DIV1
5
RES
4
CLK2-
DIV0
4
RES
3
CLK1-
DIV1
3
Preliminary Technical Data
RES
2
CLK1-
DIV0
2
RES
1
MCLK-
SEL1
1
TxMUX
0
MCLK-
SEL0
0

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