adav802 Analog Devices, Inc., adav802 Datasheet - Page 17

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
HARDWARE MODEL
The output rate of the low-pass filter of Figure 10 would be the
interpolation rate, 2
rate of 201.3 GHz is clearly impractical, not to mention the
number of taps required to calculate each interpolated sample.
However, since interpolation by 2
samples between each f
low-pass FIR filter are by zero. A further reduction can be
realized by the fact that since only one interpolated sample is
taken at the output at the f
to be performed per f
64-tap FIR filter for each f
the images caused by the interpolation. The difficulty with the
above approach is that the correct interpolated sample needs to
be selected upon the arrival of f
convolutions per f
must be measured with an accuracy of 1/201.3 GHz = 4.96 ps.
Measuring the f
frequency is clearly impossible; instead, several coarse
measurements of the f
over time.
Another difficulty with the above approach is the number of
coefficients required. Since there are 2
with a 64-tap FIR filter, there needs to be 2
coefficients for each tap, which requires a total of 2
coefficients. To reduce the amount of coefficients in ROM, the
SRC stores small subset of coefficients and performs a high
order interpolation between the stored coefficients. So far the
above approach works for the case of f
the case when the output sample rate, f
input sample rate, f
IN
f S_IN
Figure 11. Frequency Domain of the Interpolation and Resampling
FREQUENCY DOMAIN OF SAMPLES AT f S_IN
FREQUENCY DOMAIN OF THE INTERPOLATION
FREQUENCY DOMAIN OF f S_OUT RESAMPLING
FREQUENCY DOMAIN AFTER
RESAMPLING
SIN(X)/X OF ZER0-ORDER HOLD
INTERPOLATE
BY N
S_OUT
S_OUT
S_IN
20
period with a clock of 201.3 GHz
S_OUT
× 192000 kHz = 201.3 GHz. Sampling at a
, the ROM starting address, input data,
S_OUT
period, the arrival of the f
S_IN
S_OUT
S_OUT
period instead of 2
sample, most of the multiplies in the
clock period are made and averaged
LOW-PASS
FILTER
sample is sufficient to suppress
rate, only one convolution needs
S_OUT
20
involves zero-stuffing 2
. Since there are 2
20
2 20 × f S_IN
S_OUT
S_OUT
possible convolutions
ZERO-ORDER
20
, is less than the
> f
2 20 × f S_IN
2 20 × f S_IN
polyphase
HOLD
20
f S_IN
S_IN
convolutions. A
S_OUT
. However, in
26
20
clock
f S_OUT
possible
20
Rev. Pr G | Page 17 of 53
OUT
−1
and the length of the convolution must be scaled. As the input
sample rate rises over the output sample rate, the anti-aliasing
filter’s cutoff frequency has to be lowered because the Nyquist
frequency of the output samples is less than the Nyquist
frequency of the input samples. To move the cutoff frequency of
the antialiasing filter, the coefficients are dynamically altered
and the length of the convolution is increased by a factor of
(f
This technique is supported by the Fourier transform property
that if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of
decimation is simply limited by the size of the RAM.
THE SAMPLE RATE CONVERTER ARCHITECTURE
The architecture of the sample rate converter is shown in Figure
12. The sample rate converter’s FIFO block adjusts the left and
right input samples and stores them for the FIR filter’s
convolution cycle. The f
to the FIFO block and the ramp input to the digital servo loop.
The ROM stores the coefficients for the FIR filter convolution
and performs a high order interpolation between the stored
coefficients. The sample rate ratio block measures the sample
rate for dynamically altering the ROM coefficients and scaling
of the FIR filter length as well as the input data. The digital
servo loop automatically tracks the f
and provides the RAM and ROM start addresses for the start of
the FIR filter convolution.
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample
rate converter and the scaling of the input data by the sample
rate ratio before storing the samples in the RAM. The input data
is scaled by the sample rate ratio because as the FIR filter length
of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(f
data for muting and unmuting of the SRC.
The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the f
counter is added to prevent the RAM read pointer from ever
overlapping the write address. The minimum offset on the SRC
S_IN
S_OUT
RIGHT DATA IN
LEFT DATA IN
COUNTER
/f
/f
S_OUT
f S_IN
S_IN
f S_OUT
Figure 12. Architecture of the Sample Rate Converter
).
) when f
f S_IN
S_OUT
SAMPLE RATE RATIO
SAMPLE RATE
SERVO LOOP
DIGITAL
RATIO
S_IN
< f
FIFO
S_IN
counter provides the write address
. The FIFO also scales the input
EXTERNAL
RATIO
S_IN
and f
ROM A
ROM B
ROM D
ROM C
FIR FILTER
S_OUT
sample rates
L/R DATA OUT
ADAV802
ORDER
INTERP
HIGH
801-0011
S_IN