adav802 Analog Devices, Inc., adav802 Datasheet - Page 36

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
Table 46. Preamble-D MSB Register (Read Only)
ADDRESS = 0010110
PRE_D15-08
Table 47. Preamble-D LSB Register (Read Only)
ADDRESS = 0010111
PRE_D07-00
Table 48. Receiver Error Register (Read Only)
ADDRESS = 0011000
RxValidity
Emphasis
NonAudio
NonAudio Preamble
CRCError
NoStream
BiPhase/Parity
Lock
PRE_D15-PRE_D08
7,6,5,4,3,2,1,0
The eight most significant bits of the sixteen bit Preamble-D when Nonaudio data is detected according to the
IEC60937 standard, otherwise bits show zeros. When subframe Nonaudio is used this becomes the 8 most
significant bits of the 16 bit Preamble-C of Channel B
PRE_D07-PRE_D00
7,6,5,4,3,2,1,0
The eight least significant bits of the sixteen bit Preamble-D when Nonaudio data is detected according to
the IEC60937 standard, otherwise bits show zeros When subframe Nonaudio is used this becomes the 8 most
significant bits of the 16 bit Preamble-C of Channel B
RxValidity
7
This is the VALIDITY bit in the AES3 Received stream
This bit will be set if the audio data is preemphasized. Once it has been read it will remain high and
not generate an interrupt unless it changes state
This bit will be set when Channel Status Bit 1 (Nonaudio) is set. Once it has been read it will not
generate another interrupt unless the data becomes audio or the type of nonaudio data changes
This bit will be set if the audio data is nonaudio due to the detection of a Preamble. The NonAudio
Preamble Type register will indicate what type of preamble was detected. Once read it will remain
in its state and not generate an interrupt unless it has changed state
This bit is the error flag for the channel status CRC error check. This bit will not clear until the
Receiver Error Register is read
This bit will be set if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read it
will remain high and not generate an interrupt unless its changes state.
This bit will be set if a biphase or parity error occurred in the AES3/SPDIF stream. This bit will not be
cleared until the register is read.
This bit will be set if the PLL has locked or cleared when the PLL loses lock. Once read it will remain
in its state and not generate an interrupt unless it has changed state.
Emphasis
6
Rev. Pr G | Page 36 of 53
Non-
Audio
5
NonAudio
Preamble
4
CRC-
Error
3
Preliminary Technical Data
No-
Stream
2
BiPhase/
Parity
1
Lock
0